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M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
DESCRIPTION
FEATURES
The MITSUBISHI M6MGB/T162S4BVP is a Stacked Multi * Access time Chip Package (S-MCP) that contents 16M-bits flash memory Flash Memory 90ns (Max.) and 4M-bits Static RAM in a 48-pin TSOP (TYPE-I). SRAM 85ns (Max.) * Supply voltage Vcc=2.7 ~ 3.6V 16M-bits Flash memory is a 1048576 words, 3.3V-only, and * Ambient temperature high performance non-volatile memory fabricated by CMOS W version Ta=-20 ~ 85C technology for the peripheral circuit and DINOR(DIvided * Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch bit-line NOR) architecture for the memory cell. 4M-bits SRAM is a 262144words unsynchronous SRAM fabricated by silicon-gate CMOS technology. APPLICATION M6MGB/T162S4BVP is suitable for the application of the Mobile communication products mobile-communication-system to reduce both the mount space and weight .
PIN CONFIGURATION (TOP VIEW)
A15 A14 A13 A12 A11 A10 A9 A8 A19 S-CE WE# F-RP# F-WP# S-VCC F-RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 DQ15 GND S-A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 F-VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND F-CE# A0
10.0 mm
14.0 mm
F-VCC S-VCC GND S-A-1 A0-A17 A18-A19 DQ0-DQ15 F-CE# S-CE OE# WE# F-WP# F-RP# F-RY/BY# :Vcc for Flash NC:Non Connection :Vcc for SRAM :GND for Flash SRAM :Address for SRAM :Flash/SRAM common Address :Address for Flash :Data I/O :Flash Chip Enable :SRAM Chip Enable :Flash/SRAM Output Enable :Flash/SRAM Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy
1
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
BLOCK DIAGRAM
16Mb Flash Memory
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
128 WORD PAGE BUFFER Main Block 32KW
F-VCC(3.3V)
28
Bank(II)
GND (0V)
Main Block
Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block
X-DECODER Bank(I)
32KW
16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW
ADDRESS INPUTS
Y-DECODER
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
MULTIPLEXER
CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT
F-CE# OE# WE# F-WP# F-RP#
CUI
WSM INPUT/OUTPUT BUFFERS
READY/BUSY OUTPUT
F-RY/BY# DQ15 DQ14DQ13DQ12 DQ3DQ2DQ1DQ0
4Mb SRAM
S-A-1 ADDRESS INPUT BUFFER SENSE AMP.
DATA INPUTS/OUTPUTS
ROW DECODER
A0
524288 WORD x 8 BITS
OUTPUT BUFFER
DQ 0
DQ 7
A16 A17
S-CE
DATAINPUT BUFFER
CLOCK GENERATOR
S-VCC
WE# OE#
GND
2
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
1. Flash Memory
DESCRIPTION
The Flash Memory of M6MGB/T162S4BVP is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. The Flash Memory of M6MGB/T162S4BVP is fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells.
FEATURES
Organization
.................................1048,576 word x 16bit
Boot Block M6MGB162S4BVP ........................ Bottom Boot M6MGT162S4BVP ........................ Top Boot Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II)
............................. VCC = 2.7~3.6V Supply voltage ................................
Access time
.............................. 90ns (Max.)
Power Dissipation ................................. 54 mW (Max. at 5MHz) Read (After Automatic Power saving) .......... 0.33mW (typ.) Program/Erase .................................126 mW (Max.) ................................. 0.33mW (typ.) Standby Deep power down mode ....................... 0.33mW (typ.) Auto program for Bank(I) ................................. 4ms (typ.) Program Time Program Unit .........................1word (Byte Program) (Page Program) ......................... 128word Auto program for Bank(II) ................................. 4ms (typ.) Program Time ................................. 128word Program Unit Auto Erase ................................. 40 ms (typ.) Erase time Erase Unit Bank(I) Boot Block ..................... 16Kword x 1 .............. Parameter Block 16Kword x 7 ...................... 32Kword x 28 Bank(II) Main Block Program/Erase cycles
.........................................
100Kcycles
3
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) FUNCTION
The Flash Memory of M6MGB/T162S4BVP includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the F-RP# pin is at GND, minimizing power consumption. Read The Flash Memory of M6MGB/T162S4BVP has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the Flash Memory automatically resets to read array mode. In the read array mode, low level input to F-CE# and OE#, high level input to WE# and F-RP#, and address signals to the address inputs ( A19-A0:Word Mode) output the data of the addressed location to the data input/output ( D15-D0:Word Mode). Write Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE# to low level, while F-CE# is at low level and OE# is at high level. Address and data are latched on the earlier rising edge of WE# and F-CE#. Standard micro-processor write timings are used. Deep Power-Down When F-RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, F-RP# low will abort either operation. Memory array data of the block being altered become invalid. Automatic Power-Saving (APS) The Automatic Power-Saving minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or F-CE# isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. While in this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed.
MITSUBISHI LSIs
Alternating Background Operation (BGO) The Flash Memory of M6MGB/T162S4BVP allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Read array operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. Output Disable When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When F-CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes.
4
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep powerdown, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically. Read Device Identifier Command (90H) It can normally read device identifier codes when Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE# or F-CE#. So F-CE# or OE# must be toggled every status read. Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. C)Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H) Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programing the data on the page buffer is cleared automatically. This command is valid for only Bank(I) alike Word Program. Clear Page Buffer Command (55H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes.
MITSUBISHI LSIs
DATA PROTECTION Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Program Commands A)Word/Byte Program (40H) Word program is executed by a two-command sequence. The Word Program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. The Word Program Command is Valid for only Bank(I). B)Page Program for Data Blocks (41H) Page Program for Bank(I) and Bank(II) allows fast programming of 128words/256bytes of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 129th cycle, write data must be serially inputted. Address A6-A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. The Flash Memory of M6MGB/T162S4BVP provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the Flash Memory has a master Write Protect pin (F-WP#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when F-WP# is low. When F-WP# is high, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for details. Power Supply Voltage When the power supply voltage (F-VCC) is less than VLKO, Low VCC Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of VLKO, see P.10. A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time F-Vcc reaches F-Vccmin (2.7V). During power up, F-RP#=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device. MEMORY ORGANIZATION The Flash Memory of M6MGB/T162S4BVP has one 16Kword boot block, seven 16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword main blocks for Bank(II). A block is erased independently of other blocks in the array.
5
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MEMORY ORGANIZATION
x16 ( Wordmode) F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 1C000H-1FFFFH 18000H-1BFFFH 14000H-17FFFH 10000H-13FFFH 0C000H-0FFFFH 08000H-0BFFFH 04000H-07FFFH 00000H-03FFFH A19-A0 (Word Mode) x16 ( Wordmode)
MITSUBISHI LSIs
32Kword MAIN BLOCK 35 32Kword MAIN BLOCK 34 32Kword MAIN BLOCK 33 32Kword MAIN BLOCK 32 32Kword MAIN BLOCK 31 32Kword MAIN BLOCK 30 32Kword MAIN BLOCK 29 32Kword MAIN BLOCK 28 32Kword MAIN BLOCK 27 32Kword MAIN BLOCK 26 32Kword MAIN BLOCK 25 32Kword MAIN BLOCK 24 32Kword MAIN BLOCK 23 BANK(II) BANK(I) 32Kword MAIN BLOCK 22 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20 32Kword MAIN BLOCK 19 32Kword MAIN BLOCK 18 32Kword MAIN BLOCK 17 32Kword MAIN BLOCK 16 32Kword MAIN BLOCK 15 32Kword MAIN BLOCK 14 32Kword MAIN BLOCK 13 32Kword MAIN BLOCK 12 32Kword MAIN BLOCK 11 32Kword MAIN BLOCK 10 32Kword MAIN BLOCK 9 32Kword MAIN BLOCK 8
16Kword PARAMETER BLOCK 7 16Kword PARAMETER BLOCK 6 16Kword PARAMETER BLOCK 5 16Kword PARAMETER BLOCK 4 16Kword PARAMETER BLOCK 3 16Kword PARAMETER BLOCK 2 16Kword PARAMETER BLOCK 1
FC000H-FFFFFH
16Kword BOOT BLOCK 35
F8000H-FBFFFH 16Kword PARAMETER BLOCK 34 F4000H-F7FFFH 16Kword PARAMETER BLOCK 33
BANK(I)
F0000H-F3FFFH 16Kword PARAMETER BLOCK 32 EC000H-EFFFFH 16Kword PARAMETER BLOCK 31 E8000H-EBFFFH 16Kword PARAMETER BLOCK 30 E4000H-E7FFFH 16Kword PARAMETER BLOCK 29 E0000H-E3FFFH 16Kword PARAMETER BLOCK 28 D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH A19-A0 (Word Mode)
32Kword MAIN BLOCK 27 32Kword MAIN BLOCK 26 32Kword MAIN BLOCK 25 32Kword MAIN BLOCK 24 32Kword MAIN BLOCK 23 32Kword MAIN BLOCK 22 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20 32Kword MAIN BLOCK 19 32Kword MAIN BLOCK 18 32Kword MAIN BLOCK 17 32Kword MAIN BLOCK 16 BANK(II) 32Kword MAIN BLOCK 15 32Kword MAIN BLOCK 14 32Kword MAIN BLOCK 13 32Kword MAIN BLOCK 12 32Kword MAIN BLOCK 11 32Kword MAIN BLOCK 10 32Kword MAIN BLOCK 9 32Kword MAIN BLOCK 8 32Kword MAIN BLOCK 7 32Kword MAIN BLOCK 6 32Kword MAIN BLOCK 5 32Kword MAIN BLOCK 4 32Kword MAIN BLOCK 3 32Kword MAIN BLOCK 2 32Kword MAIN BLOCK 1 32Kword MAIN BLOCK 0
16Kword BOOT BLOCK 0
Flash Memory of M6MGB162S4BVP Memory Map
Flash Memory of M6MGT162S4BVP Memory Map
6
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) BUS OPERATIONS Bus Operations for Word-Wide Mode
Pins
MITSUBISHI LSIs
Mode Read
F-CE# VIL VIL VIL VIL VIL VIH VIL VIL VIL X
OE# VIL VIL VIL VIL VIH X 2) VIH VIH VIH X
WE# VIH VIH VIH VIH VIH X VIL VIL VIL X
F-RP# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL
DQ0-15 Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z
F-RY/BY# VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z)
Array Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down
1) X at F-RY/BY# is VOL or VOH(Hi-Z). *The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition. 2) X can be VIH or VIL for control pins.
7
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
SOFTWARE COMMAND DEFINITION Command List
1st bus cycle Command Mode Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Word Program 5) Page Program 7) Single Data Load to Page Buffer 5) Page Buffer to Flash 5) Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address X X Bank3) X X Bank(I) 5) Bank Bank(I) 5) Bank(I) 5) Bank Bank Bank X Bank X Data
(DQ15-0)
2nd bus cycle Mode Address IA 2) Bank X WA 6) WA0 7) WA WA 8) BA 9) Data
(DQ15-0)
3rd ~129th bus cycles (Word Mode)
Mode
Address
Data
(DQ15-0)
FFH 90H 70H 50H 55H 40H 41H 74H 0EH 20H B0H D0H 71H 77H A7H
Read Read Write Write Write Write Write Write
ID 2) SRD4) D0H 1) WD 6) WD0 7) WD D0H 1) D0H 1)
Write
WAn 7)
WDn 7)
Read Write Write
BA BA X
DQ6 10) D0H 1) D0H 1)
1) In the word-wide version, upper byte data (DQ8-DQ15) is ignored. 2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code 3) Bank = Bank Address (Bank(I) or Bank(II)) : A19-A17. 4) SRD = Status Register Data 5) Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I). 6) WA = Write Address,WD = Write Data 7) WA0,WAn=Write Address, WD0,WDn=Write Data. Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit). and also A19-A7(Block Address, Page Address) must be valid. 8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid. 9) BA = Block Address : BA = Block Address : A19-A14(Bank1) A19-A15(Bank2) 10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
8
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
BLOCK LOCKING
Lock Bit F-RP# F-WP# (Internally) VIL VIH X VIL VIH X 0 1 X Write Protection Provided BANK(I) BANK(II) Note Lock Bit Boot Parameter Data Locked Locked Locked Locked Deep Power Down Mode Locked Locked Locked Locked Locked Locked Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked All Blocks Unlocked
1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H). WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0). 2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and 00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode to array read mode.
STATUS REGISTER
Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition "1" Ready Suspended Error Error Error "0" Busy Operation in Progress / Completed Successful Successful Successful -
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition. *DQ3 indicates the block status after the page programming, word programming and page buffer to flash. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
9
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code (-T162S4BVP) Device Code (-B162S4BVP)
The upper data(D15-8) is "0".
MITSUBISHI LSIs
Pins
A0 VIL VIH VIH
DQ7 0 1 1
DQ6 0 0 0
DQ5 0 1 1
DQ4 1 0 0
DQ3 1 0 0
DQ2 1 0 0
DQ1 0 0 0
DQ0 0 0 1
Hex. Data 1CH A0H A1H
ABSOLUTE MAXIMUM RATINGS
Symbol F-Vcc VI1 Ta Tbs Tstg I OUT Parameter Flash Vcc voltage All input or output voltage 1) Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
With respect to Ground
Min -0.2 -0.6 -20 -50 -65
Max 4.6 4.6 85 95 125 100
Unit V V C C C mA
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is F-VCC+0.5V which, during transitions, may overshoot to F-VCC+1.5V for periods <20ns.
CAPACITANCE
Symbol CIN COUT Parameter Input capacitance (Address, Control Pins) Output capacitance Test conditions Ta = 25C, f = 1MHz, Vin = Vout = 0V Min Limits Typ Max 8 12 Unit pF pF
Note: The value of common pins to Flash Memory is the sum of Flash Memory and SRAM.
DC ELECTRICAL CHARACTERISTICS (Ta = -20~ 85C, F-Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Symbol ILI ILO ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current F-VCC standby current Test conditions 0VVINF-VCC 0VVOUTF-VCC
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
Min
Limits Typ1)
50 0.1 5 0.1 8 2
Max 2.0 11 200 5 15 5 15 4 15 35 35 200 0.8
F-Vcc+0.5
Unit mA mA mA mA mA mA mA mA mA mA mA V V V V V V
F-VCC = 3.6V, VIN=GND or F-VCC, F-CE# = F-RP# = F-WP# = F-VCC0.3V F-VCC = 3.6V, VIN=VIL/VIH, F-RP# = VIL
F-VCC = 3.6V, VIN=GND or VCC, F-RP# =GND0.3V
F-VCC deep powerdown current F-VCC read current for Word or Byte F-VCC Write current for Word or Byte F-VCC program current F-VCC erase current F-VCC suspend current Input low voltage Input high voltage Output low voltage Output high voltage Low VCC Lock-Out voltage 2)
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = VIL, F-RP#=OE#=VIH, IOUT = 0mA
5MHz 1MHz F-VCC = 3.6V,VIN=VIL/VIH, F-CE# =WE#= VIL, F-RP#=OE#=VIH
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
- 0.5 2.0 IOL = 4.0mA IOH = -2.0mA IOH = -100mA
0.85(F-Vcc) F-Vcc-0.4
0.45
1.5
2.2
All currents are in RMS unless otherwise noted. 1) Typical values at F-Vcc=3.3V, Ta=25C 2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO. If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
10
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85C, F-Vcc = 2.7V ~3.6V) Read-Only Mode
Limits
Symbol
Parameter Min 90
F-Vcc=2.7-3.6V 90ns Typ Max 90 90 30 0 25 0 25 150 0 150
Unit
tRC ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tOH tPS
tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tOH tPHEL
Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z F-RP# low to output high-Z Output hold from F-CE#, OE#, addresses F-RP# recovery to F-CE# low
ns ns ns ns ns ns ns ns ns ns ns
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85C, F-Vcc = 2.7V ~3.6V) Write Mode (F-WE# control)
Limits F-Vcc=2.7-3.6V 90ns Typ Max
Symbol
Parameter Min 90 50 0 50 0 10 30 0 0 60 30 0 90 0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWC tAS tAH tDS tDH tOEH tRE tCS tCH tWP tWPH tGHWL tBLS tBLH tDAP tDAE tWHRL tPS
tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH tWHWL tGHWL tPHHWH tQVPH tWHRH1 tWHRH2 tWHRL tPHWL
Write cycle time Address set-up time Address hold time Data set-up time Data hold time OE# hold from WE# high Latency between Read and Write FFH or 71H Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high OE# hold to WE# Low Block Lock set-up to write enable high Block Lockhold from valid SRD Duration of auto-program operation Duration of auto-block erase operation Write enable high to F-RY/BY# low F-RP# high recovery to write enable low
4 40 150
80 600 90
ms ms ns ns
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at F-Vcc=3.3V, Ta=25C
11
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 85C, F-Vcc = 2.7V ~ 3.6V) Write Mode (F-CE# control)
Limits F-Vcc=2.7-3.6V 90ns Typ Max
Symbol
Parameter Min 90 50 0 50 0 10 30 0 0 60 30 90 90 0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWC tAS tAH tDS tDH tOEH tRE tWS tWH tCEP tCEPH tGHEL tBLS tBLH
tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL tWLEL tEHWH tELEH tEHEL tGHEL tPHHEH tQVPH
Write cycle time Address set-up time Address hold time Data set-up time Data hold time OE# hold from CE# high Latency between Read and Write FFH or 71H Write enable set-up time Write enable hold time F-CE# pulse width
F-CE# pulse width high OE# hold to F-CE# Low Block Lock set-up to chip enable high Block Lockhold from valid SRD tDAP tEHRH1 Duration of auto-program operation tDAE tEHRH2 Duration of auto-block erase operation tEHRL tEHRL F-CE# high to F-RY/BY# low tPS tPHWL F-RP# high recovery to write enable low
4 40 150
80 600 90
ms ms ns ns
Read timing parameters during command write operation mode are the same as during read-only operation mode. Typical values at F-Vcc=3.3V, Ta=25C
Erase and Program Performance
Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Min Typ 40 1.0 4 Max 600 1.8 80 Unit ms sec ms
Program Suspend Latency / Erase Suspend Time
Parameter Program Suspend Latency Erase Suspend Time
Please see page 20.
Min
Typ
Max 15 15
Unit ms ms
Vcc Power Up / Down Timing
Symbol tVCS
Please see page 13. During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during power up/down. The delay time of min.2msec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vccmin during power up/down. By holding F-RP# VIL, the contents of memory is protected during F-Vcc power up/down. During power up, F-RP# must be held VIL for min.2ms from the time F-Vcc reaches F-Vccmin. During power down, F-RP# must be held VIL until Vcc reaches GND. F-RP# doesn't have latch mode ,therefore F-RP# must be held VIH during read operation or erase/program operation.
Parameter F-RP# =VIH set-up time from Vccmin
Min 2
Typ
Max
Unit ms
12
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
F-VCC
3.3V GND tVCS VIH VIL
F-RP#
F-CE#
VIH VIL tPS tPS
WE#
VIH VIL
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
VIH
ADDRESSES ADDRESS VALID
TEST CONDITIONS FOR AC CHARACTERISTICS Input voltage : VIL = 0V, VIH = 3.0V Input rise and fall times : 5ns Reference voltage at timing measurement : 1.5V Output load : 1TTL gate + CL(30pF) or
VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL DATA VOH VOL F-RP# VIH VIL HIGH-Z tPS tCLZ tOEH tRE
tRC ta (AD) ta (CE) tDF(CE)
tDF(OE) ta (OE) tOLZ
OUTPUT VALID
tOH HIGH-Z
1.3V 1N914 3.3kW DUT CL =30pF
tPHZ
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
ADDRESSES
VIH VIL
ADDRESS VALID
tRC ta (AD) ta (CE) tRE ta (OE)
FFH or 71H
F-CE#
VIH VIL
tDF(CE)
OE#
VIH VIL tDF(OE) tOH
HIGH-Z
WE#
VIH VIL tOLZ tCLZ
OUTPUT VALID
DATA
VOH HIGH-Z VOL
Valid
tPS F-RP# VIH VIL
tPHZ
In the case of use F-CE# is Low fixed, it is allowed to define a timming specification of tRE from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE). (This is only for FFH,71H program and read)
13
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)
F-A19~F-A17, VIH A16~A7 VIL VIH A6 ~A0 VIL tWC F-CE# OE# VIH VIL tCS VIH VIL WE# VIH VIL DATA VIH VIL F-RY/BY# F-RP# VOH VOL tPS VIH VIL VIH F-WP# VIL tBLS tBLH tWP
41H 00H VALID 01H~7EH 7FH The other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
tAS tCH tWPH
tAH
ta(CE)
ta(CE) ta(OE)
tOEH
tGHWL ta(OE)
tOEH tDAP
tDS
DIN
tDH
DOUT DIN DIN SRD FFH
tWHRL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-CE# control)
F-A19~F-A17, VIH A16~A7 VIL VIH A6 ~A0 VIL tWC F-CE# OE# VIH VIL VIH VIL WE# VIH VIL DATA VIH VIL F-RY/BY# VOH VOL tPS F-RP# VIH VIL VIH F-WP# VIL tBLS tBLH tDS
41H DIN The other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
00H
VALID
01H~7EH
7FH
tAS tCEPH
tAH ta(CE) ta(OE) tOEH tGHEL tOEH tDAP
ta(CE) ta(OE)
tCEP tWS tWH
tDH
DOUT DIN DIN SRD FFH
tEHRL
14
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) AC WAVEFORMS FOR WORD PROGRAM OPERATION (WE# control) (to only BANK(I))
PROGRAM
BANK ADDRESS VALID
MITSUBISHI LSIs
VIH ADDR VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH F-RY/BY# VIL VIH F-RP# VIL VIH VIL
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
ADDRESS VALID
BANK(I) ADDRESS VALID
tWC tCS
tAS
tAH
ta(CE) ta(OE) tOEH
tCH tWP tWPH
tDS
40H DIN SRD FFH
tDH tWHRL tPS tDAP
tBLS tBLH
F-WP#
AC WAVEFORMS FOR WORD PROGRAM OPERATION (F-CE# control)
PROGRAM
BANK ADDRESS VALID
(to only BANK(I))
WRITE READ ARRAY COMMAND
VIH ADDR VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH F-RY/BY# VIL VIH F-RP# VIL VIH VIL
READ STATUS REGISTER
ADDRESS VALID
BANK(I) ADDRESS VALID
tWC
tAS
tAH
ta(CE) ta(OE)
tCEP tWS tWH tDS
40H DIN
tOEH
SRD
FFH
tDH tEHRL tPS tDAP
tBLS tBLH
F-WP#
15
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)
VIH
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL VIH F-CE# VIL tCS VIH OE# VIL VIH WE# VIL
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
tWC
tAS
tAH
ta(CE)
tCH tOEH tDAE tDH
D0H
ta(OE)
tWPH
tWP VIH DATA
20H
tDS
SRD
FFH
VIL VOH VOL tPS VIH VIL tBLS
tWHRL
F-RY/BY#
F-RP#
tBLH
F-WP#
VIH VIL
AC WAVEFORMS FOR ERASE OPERATIONS (F-CE# control)
VIH
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL VIH F-CE# VIL
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
tWC
tAS
tAH
ta(CE)
tCEP VIH OE# VIL tWS VIH WE# VIL VIH DATA
20H
tCEPH tOEH
ta(OE)
tWH tDS
D0H
tDAE tDH
SRD FFH
VIL VOH VOL tPS
tEHRL
F-RY/BY#
F-RP#
VIH VIL tBLS tBLH
F-WP#
VIH VIL
16
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address PROGRAM DATA TO ONE BANK
A19~A7
VIH VIL VIH
ARRAY READ FROM THE OTHER BANK WITH BGO
BANK ADDRESS VALID
ADDRESS VALID
VALID
VALID
A6 ~A0 VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH F-RY/BY# VIL
41H
00H
01H~7EH
7FH
VALID
VALID
tWC tCS
tAS tCH tWP tWPH
tAH
ta(CE) ta(OE) tOEH
tDS
DIN DIN DIN SRD DOUT DOUT
tDH
tWHRL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-CE# control)
Change Bank Address PROGRAM DATA TO ONE BANK
A19~A7
VIH VIL VIH
ARRAY READ FROM THE OTHER BANK WITH BGO
BANK ADDRESS VALID
ADDRESS VALID
VALID
VALID
A6 ~A0
00H
01H~7EH
7FH
VALID
VALID
VIL VIH VIL
tWC
tAS tCEPH
tAH
ta(CE) ta(OE) tOEH
F-CE#
OE#
VIH VIL
tCEP tWS
WE#
VIH VIL
tCH tDS
41H DIN DIN DIN SRD DOUT DOUT
DATA
VIH VIL VIH
tDH
tEHRL
F-RY/BY# VIL
17
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC WAVEFORMS FOR WORD PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address PROGRAM DATA TO BANK(I)
BANK ADDRESS VALID
VIH A19~A7 VIL VIH A6 ~A0 VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH F-RY/BY# VIL
READ STATUS REGISTER
ARRAY READ FROM BANK(II) WITH BGO
ADDRESS VALID
VALID
VALID
VALID
VALID
VALID
tWC tCS
tAS tCH tWP tWPH
tAH
ta(CE) ta(OE)
tOEH
tDS
40H DIN SRD DOUT DOUT
tDH tWHRL
AC WAVEFORMS FOR WORD PROGRAM OPERATION WITH BGO (F-CE# control)
PROGRAM DATA TO BANK(I)
BANK ADDRESS VALID
A19~A7
VIH VIL VIH
READ STATUS REGISTER
Change Bank Address ARRAY READ FROM BANK(II) WITH BGO
ADDRESS VALID
VALID
VALID
A6 ~A0
VALID
VALID
VALID
VIL VIH VIL
tWC
tAS tCEPH
ta(CE) ta(OE) tOEH
F-CE#
OE#
VIH VIL
tCEP tWS
WE#
VIH VIL VIH
tCH tDS
40H DIN SRD DOUT DOUT
DATA VIL VIH F-RY/BY# VIL
tDH tEHRL
18
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)
Change Bank Address BLOCK ERASE IN ONE BANK
BANK ADDRESS VALID
MITSUBISHI LSIs
VIH ADDRESSES VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH F-RY/BY# VIL
READ STATUS REGISTER
ARRAY READ FROM THE OTHER BANK WITH BGO
ADDRESS VALID
VALID
VALID
tWC tCS
tAS tCH tWP tWPH tOEH
tAH
ta(CE) ta(OE)
tDS
20H D0H SRD DOUT DOUT
tDH tWHRL
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-CE# control)
Change Bank Address BLOCK ERASE IN ONE BANK
BANK ADDRESS VALID
VIH ADDRESSES VIL F-CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH F-RY/BY# VIL
READ STATUS REGISTER
READ DATA FROM THE OTHER BANK WITH BGO
ADDRESS VALID
VALID
VALID
tWC
tAS tCEPH
tAH
ta(CE) ta(OE)
tCEP tWS
tOEH tCH tDS
20H D0H SRD DOUT DOUT
tDH tEHRL
19
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) AC WAVEFORMS FOR SUSPEND OPERATION (WE# control)
VIH
ADDRESSES
READ STATUS REGISTER
MITSUBISHI LSIs
VIL VIH F-CE# VIL
BANK ADDRESS VALID
BANK ADDRESS VALID
tAS
tAH
ta(CE)
tCS VIH OE# VIL VIH WE# VIL tWP VIH DATA
B0H
tCH tOEH Program Suspend Latency
ta(OE)
S.R.6,7=1
VALID SRD
VIL VOH VOL VIH VIL VIH tBLS tBLH
F-RY/BY#
F-RP#
F-WP#
VIL
AC WAVEFORMS FOR SUSPEND OPERATION (F-CE# control)
VIH
ADDRESSES BANK ADDRESS VALID
READ STATUS REGISTER
BANK ADDRESS VALID
VIL tAS VIH F-CE# VIL VIH OE# VIL VIH WE# VIL VIH DATA
B0H
tAH tCEP
ta(CE)
ta(OE) tOEH Program Suspend Latency tWS tWH S.R.6,7=1
VALID SRD
VIL VOH VOL VIH VIL VIH tBLS tBLH
F-RY/BY#
F-RP#
F-WP#
VIL
20
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
MITSUBISHI LSIs
LOCK BIT PROGRAM FLOW CHART
START
SR.4 =1 and SR.5 =1 ? NO
WRITE 77H YES COMMAND SEQUENCE ERROR WRITE D0H BLOCK ADDRESS
SR.5 = 0 ? NO YES
BLOCK ERASE ERROR SR.7 = 1 ? NO YES
SR.4 = 0 ? NO YES
PROGRAM ERROR (PAGE, LOCK BIT) SR.4 = 0 ? NO YES
LOCK BIT PROGRAM FAILED
SR.3 = 0 ? NO YES SUCCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
LOCK BIT PROGRAM SUCCESSFUL
BYTE PROGRAM FLOW CHART
START
PAGE PROGRAM FLOW CHART
START
WRITE 40H WRITE 41H
WRITE ADDRESS , DATA
n=0
STATUS REGISTER READ
WRITE ADDRESS n, DATA n
n = n+1
SR.7 = 1 ?
NO
WRITE B0H ?
NO
n = FFH ? or n = 7FH ? YES
NO
YES
YES
STATUS REGISTER READ
FULL STATUS CHECK IF DESIRED
SUSPEND LOOP WRITE D0H
YES SR.7 = 1 ? NO WRITE B0H ? NO
PAGE PROGRAM COMPLETED
* Word program is admitted to only BANK(I).
YES
YES
FULL STATUS CHECK IF DESIRED
SUSPEND LOOP WRITE D0H
YES
PAGE PROGRAM COMPLETED
21
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) CLEAR PAGE BUFFER
START
MITSUBISHI LSIs
SUSPEND / RESUME FLOW CHART
START
WRITE B0H WRITE 55H STATUS REGISTER READ WRITE D0H SR.7 = 1? NO PAGE BUFFER CLEAR COMPLETED YES
SUSPEND
SR.6 =1?
SINGLE DATA LOAD TO PAGE BUFFER
YES START WRITE FFH
NO
PROGRAM / ERASE COMPLETED
WRITE 74H
READ ARRAY DATA
WRITE ADDRESS , DATA
DONE READING ? YES
NO
DONE LOADING?
NO
WRITE D0H
RESUME
YES SINGLE DATA LOAD TO PAGE BUFFER COMPLETED
OPERATION RESUMED
* The bank address is required when writing this command. Also, there is no need to suspend the erase or program operation when reading data from the other bank. Please use BGO function.
PAGE BUFFER TO FLASH
START
BLOCK ERASE FLOW CHART
START
WRITE 20H WRITE 0EH WRITE D0H BLOCK ADDRESS WRITE D0H PAGE ADDRESS STATUS REGISTER READ STATUS REGISTER READ
NO NO SR.7 = 1 ? WRITE B0H ? NO SR.7 = 1 ?
WRITE B0H ?
NO
YES FULL STATUS CHECK IF DESIRED
YES FULL STATUS CHECK IF DESIRED
YES
SUSPEND LOOP WRITE D0H
YES
SUSPEND LOOP WRITE D0H
PAGE BUFFER TO FLASH COMPLETED YES
BLOCK ERASE COMPLETED
22
Sep. 1999 , Rev.2.0
OPERATION STATUS and EFFECTIVE COMMAND
23 Clear Status Register
50H
Read/Standby State Read Status Register
90H 70H 70H 90H 71H 71H FFH FFH 70H 71H
Read Device Identifier
90H FFH
Read Lock Status
Read Array
Setup State Clear Page Buffer Setup
D0H 55H 74H
WD 0EH 41H 40H 77H
20H
A7H
Single Data Load to Page Buffer Setup
Page Buffer to Flash Setup
Page Program Setup
Byte Program Setup
WD D0H
Lock Bit Program Setup
Block Erase Setup
D0H
Erase All Unlocked Blocks Setup
OTHER
OTHER
D0H
Internal State
WDi i=0-127
OTHER
OTHER D0H
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
Program & Verify
Ready
Erase & Verify Read Status Register
D0H B0H B0H D0H
Read Status Register
M6MGB/T162S4BVP
Suspend State
Change Bank Address
Read Status Register
Change Bank Address
FFH 70H
70H
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
Read State with BGO Read Array
(From The Other Bank)
Read Array
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
2. SRAM
The SRAM of M6MGB/T162S4BVP is organized as 524,288-word by 8-bit. These devices operate on a single +2.7~3.6V powersupply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs , S-CE , WE# and OE#. Each mode is summarized in the function table. A write operation is executed whenever the low level WE# overlaps with the high level S-CE. The address S-A-1~A17 must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting WE# at a high level and OE# at a low level while S-CE are in an active state(S-CE=H). When setting S-CE at a low level,the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in ahigh-impedance state, allowing OR-tie with other chips and memory expansion by S-CE. The power supply current is reduced as low as 0.3mA(25 C,typical), and the memory data can be held at +2V powersupply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S-CE L H H H WE# X L H H OE# X X L H Mode
Non selection
DQ0~7
Icc Standby Active Active Active
High-Z Din Dout High-Z
Write Read
24
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
ABSOLUTE MAXIMUM RATINGS
Symbol
S-Vcc VI VO Pd Ta Tstg
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature
Conditions With respect to GND With respect to GND With respect to GND Ta=25 C W-version
Ratings
Units
-0.5* ~ +4.6 -0.5* ~ S-Vcc + 0.5 0 ~ S-Vcc 700 - 20 ~ +85 - 65 ~ +150
V mW C C
* -3.0V in case of AC (Pulse width< 30ns) =
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage 1 IOH= -0.5mA High-level output voltage 2 IOH= -0.05mA Low-level output voltage Input leakage current Output leakage current Active supply current ( AC,MOS level ) Active supply current ( AC,TTL level ) Conditions
( S-Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Min Typ Max
S-Vcc+0.3V
Units
VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2
2.2 -0.3 * 2.4
S-Vcc-0.5V
0.6 V 0.4 1 1
IOL=2mA VI =0 ~ S-Vcc
S-CE=VIL or OE#=VIH, VI/O=0 ~ S-Vcc
S-CE = S-Vcc-0.2V other inputs < 0.2V or > S-Vcc-0.2V = = Output - open (duty 100%) S-CE=VIH other pins =VIH or VIL Output - open (duty 100%)
<
mA
f= 10MHz f= 1MHz f= 10MHz f= 1MHz +70 ~ +85 C
-
50 7 50 7 1 0.3 -
70 15 70 15 40 20 3.6 1.2 0.5
mA
Icc3
Stand by supply current ( AC,MOS level )
S-CE < 0.2V = Other inputs=0~S-Vcc
+40 ~ +70 C -W +25 ~ +40 C - 20 ~ +25 C
mA
Icc4 Stand by supply current
( AC,TTL level )
S-CE=VIL Other inputs= 0 ~ S-Vcc
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for S-Vcc=3.0V and Ta=25 C
* -3.0V in case of AC (Pulse width< 30ns) =
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Min Typ Max Units
CI CO
10 10
pF
Note: The value of common pins to SRAM is the sum of Flash Memory and SRAM.
25
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
AC ELECTRICAL CHARACTERISTICS
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply voltage Input pulse Input rise time and fall time Reference level
2.7V~3.6V VIH=2.4V,VIL=0.4V 5ns VOH=VOL=1.5V
Transition is measured 500mV from steady state voltage.(for ten,tdis)
1TTL DQ CL
Including scope and jig capacitance
Output loads
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after S-CE low Output disable time after OE# high Output enable time after S-CE high Output enable time after OE# low Data valid time after address
SRAM
Units Max 85 85 45 30 30 ns ns ns ns ns ns ns ns ns
Min 85
ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tV(A)
10 5 10
(3) WRITE CYCLE
Limits Symbol Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to WE# Chip select setup time Data setup time Data hold time Write recovery time Output disable time from WE# low Output disable time from OE# high Output enable time from WE# high Output enable time from OE# low Min 85 60 0 70 70 35 0 0
SRAM
Units Max ns ns ns ns ns ns ns ns ns ns ns ns
tCW tw(W) tsu(A) tsu(A-WH) tsu(CE) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
30 30 5 5
26
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
(4)TIMING DIAGRAMS Read cycle
S-A-1~A17 ta(A) tv (A) tCR
S-CE
(Note3)
ta(CE) tdis (CE) ta (OE)
(Note3) (Note3)
OE#
ten (OE) ten (CE)
tdis (OE)
(Note3)
WE# = "H" level
DQ0~7
VALID DATA
Write cycle ( WE# control mode )
tCW S-A-1~A17 tsu (CE)
S-CE
(Note3)
tsu (A-WH)
(Note3)
OE# tsu (A) WE# tdis(OE) DQ0~7
DATA IN STABLE
tw (W) tdis (W)
trec (W) ten(OE) ten (W)
tsu (D)
th (D)
27
Sep. 1999 , Rev.2.0
M6MGB/T162S4BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package)
MITSUBISHI LSIs
Write cycle (S-CE control mode)
tCW S-A-1~A17 tsu (A) S-CE
(Note4)
tsu (CE)
trec (W)
WE#
(Note3)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ0~7
Note 3: Hatching indicates the state is "don't care". Note 4: When the falling edge of WE# is simultaneously or priorto the rising edge of S-CE, the outputs are maintained in the high impedance state. Note 5: Don't apply inverted phase signal externally when DQ pin is in output mode.
28
Sep. 1999 , Rev.2.0

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